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[VHDL-FPGA-Verilog] VHD_Veri_spi

Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
Platform: | Size: 13312 | Author: 中国 | Hits:

[VHDL-FPGA-Verilog] spi_latest.tar

Description: spi接口 verilog版本, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:-spi interface, verilog version, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:
Platform: | Size: 2624512 | Author: shen | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] Q8051

Description: A 1T51 core which contain 16 verilog files. this mcu core consiste with standard 51
Platform: | Size: 34816 | Author: 艾瑞庭 | Hits:

[VHDL-FPGA-Verilog] a_vhdl_8253_timer_latest.tar

Description: 一个apb总线控制8253的verilog源代码，符合标准的amba 2.0的总线规范-A apb bus control 8253 of the verilog source code, amba 2.0 standard bus specification
Platform: | Size: 107520 | Author: 蔡搏 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL-Coding-Reuse-Standard

Description: Verilog HDL Coding 语言介绍书籍，主要集中于复用这块-Verilog HDL Coding language to introduce books, this focuses on reuse
Platform: | Size: 198656 | Author: 苏蔚 | Hits:

[VHDL-FPGA-Verilog] Introduction-to-Verilog

Description: Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, -Introduced in 1984 by Gateway Design Automation n 1989 Cadence purchased Gateway (Verilog-XL simulator) n 1990 Cadence released Verilog to the public n Open Verilog International (OVI) was formed to control the language specifications. n 1993 OVI released version 2.0 n 1993 IEEE accepted OVI Verilog as a standard, Verilog 1364
Platform: | Size: 191488 | Author: zhujizhen | Hits:

[VHDL-FPGA-Verilog] aes-core

Description: Verilog编写的美国标准加密算法AES的硬件实现包含完整代码及测试程序。- Verilog the compilation American standard encryption algorithm AES hardware realizes contains the complete code and the test order.
Platform: | Size: 88064 | Author: fujiwei | Hits:

[File Format] Verilog-HDL-standard

Description: VERILOG的编码设计规范，使你的程序容易被理解，阅读和维护-VERILOG coding design specifications, to make your program easier to understand, read and maintain
Platform: | Size: 6144 | Author: 顾善昉 | Hits:

[VHDL-FPGA-Verilog] IEEE-standard-Verilog-HDL1364-2001

Description: verilog 硬件描述语言 golden版-verilog hardware descriptor language golden version
Platform: | Size: 2186240 | Author: willow | Hits:

[VHDL-FPGA-Verilog] verilog-RTLevel-Synthesis

Description: 本章详细的分析了寄存器传输级综合，ieee最新标准-IEEE Standard for Verilog® Register Transfer Level Synthesis
Platform: | Size: 380928 | Author: 王凯 | Hits:

[VHDL-FPGA-Verilog] scoreboard

Description: MIPS体系结构用verilog实现的记分牌算法，标流水线-Architecture implemented using verilog scoreboard algorithm, standard line
Platform: | Size: 148480 | Author: 王垚 | Hits:

[VHDL-FPGA-Verilog] IEEE-standard-Verilog-HDL

Description: IEEE 标准 Verilog 硬件描述语言，这是IEEE 制订的verilog 标准参考文档-IEEE Standard for Verilog Hardware Description Language
Platform: | Size: 3170304 | Author: 唐小飞 | Hits:

[VHDL-FPGA-Verilog] IEEE_Standard_verilog_std_1364_1995

Description: Here is verilog standard which u may find useful! share share
Platform: | Size: 1437696 | Author: dmy | Hits:

[Other] 2005-Verilog-IEEE-Std(1364-2005)

Description: IEEE Standard for Verilog Hardware Description Language 1364-2005 verilog2005版本的标准-IEEE Standard for Verilog Hardware Description Language 1364-2005
Platform: | Size: 3185664 | Author: 赵先生 | Hits:

[VHDL-FPGA-Verilog] Prentice---Verilog.HDL_A.Guide.to.Digital.Design.

Description: Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.-Written for both experienced and new users, this book gives you broad coverage of Verilog HDL. The book stresses the practical design and verification perspective ofVerilog rather than emphasizing only the language aspects. The informationpresented is fully compliant with the IEEE 1364-2001 Verilog HDL standard.
Platform: | Size: 1723392 | Author: bom | Hits:

[VHDL-FPGA-Verilog] UART16550(Verilog)

Description: 通过各项仿真的模块代码，是一个标准的模块，可以直接使用-Through various simulation module code is a standard module, can be used directly
Platform: | Size: 11264 | Author: 阿汤哥 | Hits:

[assembly language] chao

Description: 利用有限状态机实现一般时序逻辑分析的方法； 进掌握用Verilog编写的有限状态机的标准模板-Finite state machine to achieve general sequential logic analysis method into the grasp of finite state machines using Verilog standard template
Platform: | Size: 161792 | Author: zhangchao | Hits:

[Other] Freescale-Verilog-HDL-Coding

Description: Verilog HDL Coding Semiconductor Reuse Standard
Platform: | Size: 188416 | Author: 陈志伟 | Hits:

[Other] Verilog-

Description: verilog硬件描述语言，从基础到标准，包含很多经典设计样例-verilog hardware description language, from basic to standard, classic design contains many examples
Platform: | Size: 5329920 | Author: liuxiao | Hits:
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